Domino SRAMs are a particular class of static random-access memories, or SRAMs. SRAMs are generally capable of retaining information nearly indefinitely, as long as power is supplied, as opposed to dynamic random-access memories, or DRAMs, which must be refreshed periodically. SRAMs typically employ memory cells based on cross-coupled inverters or similar circuit arrangements. In contrast with DRAMs, which may only require one transistor per bit, SRAMs require a number of transistors which may vary from three to eight, depending on the required functionality, performance and area limitations, fabrication process, etc.
SRAMs are organized along rows (wordlines) and columns (bitlines). Rows of memory cells are activated through wordlines and data is read and written through bitlines. In standard SRAMs, a large number of cells (e.g., 128 cells) are typically connected to a single bitline. Therefore, each cell must drive a substantial parasitic capacitance, which increases read time and power consumption. To speed up the reading process, sense amplifiers are connected to the bitlines to detect small voltage swings. This allows for reading data before the bitlines experience a complete voltage transition of the order of the supply voltage. However, sense amplifiers also contribute to power consumption and consume chip area.
Examples of domino SRAMs are disclosed in U.S. Pat. Nos. 5,668,761, 5,729,501 and 6,657,886, assigned to the assignee of this application and incorporated herein by reference. In essence, the long global bitlines of a standard SRAM are partitioned into a number of short local bitlines, each connected to a cell group including a small number of cells, e.g., 4 to 16 cells. Each local bitline constitutes a node of a dynamic circuit, which is precharged to the supply voltage and discharged to ground by the memory cell's transistors. This dynamic design replaces the sense amplifier of a standard SRAM. This design style is called “domino logic” since the transition from high to low voltages at one node typically triggers more transitions down the signal path, as in a chain of dominos.
The simplification of the read path in domino SRAMs achieves higher performance and lower power consumption as compared to standard SRAMs. The small parasitic capacitance associated with each local bitline allows the cell transistors to drive large voltage swings in a short time. The large voltage swings allow single-ended sensing, which reduces the effective total capacitive load, and associated power consumption, by about 50% during readout. Moreover, single-ended sensing may be accomplished by simple local evaluation circuits, such as inverters, as opposed to complex sense amplifiers which are required for differential sensing. Each local evaluation circuit detects voltage transitions on a single local bitline. Signals from all the local evaluation circuits may be combined, e.g., by a hierarchical OR tree, to read the data out to the peripheral circuitry. The elimination of sense amplifiers and the reduction of charging/discharging currents allows a substantial improvement of the power-delay product of domino SRAMs as compared to standard SRAMs.
Most existing domino SRAM designs are inherently capable of activating only a single wordline at a time, and therefore the domino SRAM can only write a single word of data during each write cycle. This may be a disadvantage, for example, in array built-in self test (ABIST) designs. An ABIST controller may be required to initialize a complete array. With a single-word write capability, writing each and every cell in the memory array requires many write cycles. Therefore, single-word writing causes long ABIST test times and a consequent increase in the manufacturing cost of integrated circuits.
Known techniques to implement multi-word write operations also have drawbacks. For example, some SRAM architectures include a reset functionality at the memory cell level. However, this requires additional devices in each cell, which also leads to increased chip area and requires special design considerations.